FPGA-based CCD signal acquisition and transmission system design

In order to facilitate the analysis and processing of optical signals, an FPGA-based CCD signal acquisition and data transmission system is designed in this work. The system uses an FPGA as the main control device, the TCD1304DG/AP chip as the optical signal detector, and the CYUSB3KIT-003 development board product by Cypress for data transmission. Verilog and Python languages are employed for modular design and on-board verification. Through the coordination of each module, the system successfully achieves CCD signal data acquisition and transmission.


Principle of spectrometer
The classical spectrometer system, known as the Czerny-Turner spectrometer or C-T structure spectrometer, is depicted in Fig. 1.This spectrometer typically comprises some components such as an optical fiber, incident slit, collimating objective, diffraction grating, converging objective, sensor, and other elements 16 .Among these components, the most important one is sensor which converts the optical signal into the corresponding electrical

Signal processing circuit
The output signal from the CCD detector needs to be converted from analog to digital before it can be processed by the FPGA.This is because the FPGA requires digital input signals, while the CCD detector produces analog signals.In this design, the AX7Z010 development board which features a four-way AD input port is utilized.Two of these ports are dedicated to external analog signal acquisition and conversion, while the other two are used for measuring various parameters within the development board.
One of the ports is applied to acquiring external signals through the SMA interface input.After the signal is acquired, it is converted into differential signals within the XADC module of the FPGA, followed by data www.nature.com/scientificreports/processing.The FPGA processing signal model is illustrated in Fig. 4. The voltage value is represented as a 16-bit binary value obtained from the output, and the relationship between the voltage value and the ADC code is given by the formula: Once the 16-bit number is obtained after the analog-to-digital (AD) conversion, it will be stored in RAM sequentially in accordance with its corresponding address.After the exposure is completed, the data stored in RAM will be sent to the host computer in the order of the address.Upon receiving the transmission instruction from the host computer, the AD-converted data will be processed in the host computer.By applying the voltage calculation formula to the received data, the voltage value of the corresponding pixel can be determined.

Data transmission circuit
The FPGA needs to transmit the CCD signal data to the host computer for better visualization and analysis of the collected data.For this purpose, the data transmission module is employed, which is based on Cypress's CYUSB3KIT-003 development board.The logical block diagram of the board is depicted in Fig. 5.The board's functionality conforms to the USB 3.1 specification version 1.0 (TID # 340800007), meeting the requirements for USB 3.1 Gen 1 and USB 2.0.To facilitate data transfer, the programmable interface (GPIF II) of the development

System software design
Based on the introduction of Chapter 3, the overall software design can be categorized into four modules: driver module, data processing module, data transmission module, and host computer module.These modules fulfill different functions in the system.The driver module is responsible for controlling the TCD1304DG chip.It provides the necessary commands and instructions to configure and operate the chip effectively.The data processing module primarily focuses on converting the signals collected by the TCD1304DG into analogto-digital (AD) format.The converted data is then stored in the FPGA's RAM.At the same time, the module sends corresponding handshake instructions to the host computer for establishing synchronization.The data transmission module operates as follows: Upon receiving instructions from the host computer, it follows the integration time and the number of samples specified in the instructions.During this period, the host computer continuously accesses the FPGA's working state.
The module ensures that the data transfer aligns with the specified integration time and sampling requirements.The data transfer module functions as follows: After receiving instructions from the host computer, it processes the integration time and sampling times specified in the instructions.During the working period, the host computer continuously monitors the FPGA's working state.Once the CCD exposure time is completed, the module sends an end instruction to the host computer.Subsequently, the host computer can send a receive data instruction to the FPGA.Upon receiving the corresponding instruction, the FPGA transfers the data stored in the RAM to the host computer based on the provided address.The data which is processed on the host computer side is carried out according to the voltage calculation formula described in Chapter 3. The host computer performs calculations and further processing on the received data on the basis of the voltage calculation formula outlined in Chapter 3.Among these modules, the first three are compiled by the Verilog programming language, while the host computer module is implemented by Python.Figure 6 illustrates the overall design block diagram, providing an overview of the system's components and their interconnections.

Driver module
There are three control pins of the TCD1304DG: V SH , V ICG , and V ϕM .As discussed in Chapter 3, V ϕM serves as the fundamental master clock signal for the entire system, V ICG is responsible for charge reset, and V SH controls the integration time.The integration time duration is determined by the time interval between two falling edges of V SH when V ICG is at a low level.
The output time of the TCD1304DG refers to the time which takes for the CCD to output data values corresponding to all the pixels in the array.The key aspect of this design is controlling the CCD's acquisition process by managing the timing of V SH , V ICG , and V ϕM .The specific timing diagram can be found in Fig. 7.
According to the requirements of the official data sheet, the timing difference between V SH , V ICG , and V ϕM has strict requirements, and once it exceeds the requirements, the TCD1304DG will cut off the output, so the constraints of these three in the process of designing must be strictly referenced to the requirements in the data sheet, and the specifics are shown in Table 1 and Fig. 8.
In this design, the V ϕM period is set to 2 MHz.The time parameters are as follows: t1 is 5000 ns, t2 is 500 ns, and t3 is 2500 ns.Based on these values, we can determine that the low pulse time of V_ICG in a single pulse is 8000 ns.Additionally, each pixel data output requires 4 cycles of V ϕM .Therefore, the total period of V_ICG can be calculated as follows: 3648 * (500 * 4) + 8000 = 7, 304, 000ns.www.nature.com/scientificreports/Therefore, in the design of V SH , V ICG and V ϕM , it is possible to use one counter for the first two signals, while a separate counter is used for V ϕM to maintain code simplicity.The V SH signal lags behind V ICG by 500 ns, and their respective pulse widths are set according to the provided table.However, the period of both signals is the same, which is 7.304 ms.As for V_φM, it was previously set to 2 MHz, corresponding to a period of 500 ns.The resulting timing diagrams for V SH , V ICG and V ϕM are depicted in Fig. 9a-c.
From Fig. 9a-c, it is evident that the timings of t1, t2, t3, and t4 between V SH , V ICG , and V ϕM align precisely with the expected set values.

Data processing modules
The main function of the module is to transmit the analog voltage value from the TCD1304DG to the FPGA's integrated XADC (XILINX Analog-to-Digital Converter) for analog-to-digital conversion.This is achieved through the XADC input interface on the AXC7Z010 expansion board.During the analog-to-digital conversion process, it is important to consider the maximum sampling rate of the ADC module.This limit determines the maximum speed at which the ADC can perform conversions 18 .According to Nyquist's Law of Sampling, the frequency of the sampled signal cannot exceed half of the ADC's sampling rate when using the ADC for data sampling 19 .From the previous section, it was determined that the TCD1304DG takes four V ϕM cycles to output the data value of a single pixel, with a V ϕM frequency of 2 MHz.Therefore, the dual 12-bit 1 MSPS (Mega Samples Per Second) analog-to-digital converters available in the 7-series FPGAs and Zynq-7000's SOC XADC can be utilized for the data conversion of TCD1304DG, given a master clock V ϕM of 2 MHz.
The use of this 7 series XADC in Verilog requires the use of an official IP core, which can be used after a simple configuration of the XADC.The IP core interface schematic for the XADC is shown in Fig. 10.
It is important to note the interface "s_drp" in the "daddr_in" when working with the XADC.This interface is responsible for converting the channel address.Each different address corresponds to different conversion data.The specific registers corresponding to each address are depicted in Fig. 11.
According to the register address corresponding to the analog signal access channel and setting the appropriate enable signals for conversion, a 16-bit data can be obtained.This data represents the current analog signal converted by the XADC.The upper 12 bits of the data contain the conversion result, which is the most significant part.The lower 4 bits of the data, known as the unquoted data, can be used for techniques such as quantization or filtering, so as to enhance the resolution.

Data transfer module
The data transfer module in this design utilizes Cypress's CYUSB3KIT-003 for high-speed USB 3.0 transmission.For instance, in Si Yong Fu's work 20 , USB2.0 was used for the TCD1304DG acquisition work.However, it's worth noting that USB3.0 (480 Mbps) offers significantly faster data transmission compared to USB2.0 (4.8 Gbps).This increased speed in CCD data transmission can have a substantial impact on reducing the time-consuming burden of data processing by the host computer software, particularly in spectrometer design.The control mode is implemented through Cypress's programmable interface called GPIF II, which offers various operating modes.In this design, the FIFO slave device operating mode is adopted.The schematic of the synchronous slave device interface is depicted in Fig. 12.
The interface of CYUSB3KIT-003 is controlled by FPGA for data transfer purpose, and its synchronous slave device FIFO read timing diagram as well as write timing diagram are shown in Fig. 13a,b; When reading data from the FPGA to the CYUSB3KIT-003, it is necessary to stabilize the FIFO address first.Then, the SLCS and SLOE signals should be pulled down.It is important to note that SLOE is an output enable signal, and when it is high, no operation on the data bus will be executed.After that, the SLRD signal should be pulled down, allowing the FPGA to read the data transmitted through the CYUSB3KIT-003 data bus.
When writing data from the FPGA to the CYUSB3KIT-003, it is crucial to specify the FIFO address and pull down the SLCS signal.Subsequently, the SLWR signal should be pulled down, enabling the internal FIFO of the CYUSB3KIT-003 to sequentially store the data from the data bus with the assistance of the PCLK clock signal.
Concerning the CYUSB3KIT-003, it is important to note its multifunctionality, allowing it to serve as both a master and slave device.Therefore, in the design, it requires programming of its internal ARM and GPIF II interfaces.The logic diagram and state diagram of its GPIF II interface are displayed in Fig. 14a,b respectively.In this work, the PCLK was set as 100 MHz.Based on the GPIF II interface logic diagram and the synchronous slave device read/write timing diagram for FPGA programming, the timing design of each corresponding IO port signal yields the results presented in Fig. 15a-c.To ensure accurate verification of the transmission process, a specific approach is employed.When the FPGA reads data from the CYUSB3KIT-003, the CYUSB3KIT-003 transmits the data to the FPGA based on the 00-0F cycle, Fig. 15b illustrates the captured data of the USB module with the FPGA in the logic analyzer, demonstrating that SLCS, SLOE, SLRD are pull down, while flag_c and flag_d are pull up after the data in accordance with the 00-0F cycle, the observed result aligns with the expected outcome.However, when the FPGA writes data to the CYUSB3KIT-003, a register named "out_data1" is configured in the FPGA to store the data.This register is then connected to the data bus of the CYUSB3KIT-003. Figure 15c depicts the change in the "usb_data" value with www.nature.com/scientificreports/respect to "out_data1" after SLWR is pulled low and flag_a and flag_b are pulled high.This process demonstrates that the transmitted data matches the data of the FPGA after confirming the completeness and accuracy of the timing and logic interfaces between the FPGA and CYUSB3KIT-003.

Experimental results
After completing the merging of all sub-modules, including the top-level module, the integrity of the entire design began to test.Started from placing the TCD1304DG under a light source.The output of the TCD1304DG was connected to the input of the oscilloscope.Next, the TCD1304DG was placed in a shady environment, and use black adhesive tape to cover threequarters of it.From a distance of 10 cm, the TCD1304DG was illuminated vertically by a light source.The waveforms are observed and recorded under these conditions.The results of the testing process, along with the recorded waveforms, can be found in Fig. 16.
From the waveforms, it is evident that the output of the TCD1304DG exhibits a stepped pattern.This behavior can be attributed to the fact that only one-fourth of the sensor is illuminated by the light source.Consequently, the output is changed from a value close to three-fourths of its full range.
Following the normal measurement of the TCD1304DG's output, it is connected to the AD input on the FPGA expansion board to verify the expected data that is displayed on the host computer.The upper computer program, coded in Python, utilizes the official USB driver library provided by Cypress to establish the USB driver for the host computer.This program receives data transmitted from the FPGA and converts each pair of data bits into the corresponding voltage value.The data is then graphed on the window interface using the matplotlib library.The results of this process are illustrated in Fig. 17 and 17, it becomes evident that the waveforms displayed in both figures are consistent.This observation serves as the evidence for the integrity of the XADC analog-to-digital converter module, the serial transmitter module, and the timing control of the TCD1304DG, the accuracy of data reading as well.
Figure 18 depicts the captured packet data from each model of the ILA logic analyzer during the process of data transmission.In this figure, "out_data1" represents the data which is read from the RAM, "transfer_data" corresponds to the transmitted data, and the signals A, B, C, and D represent the FLAG flag bits of the CYUS-B3KIT-003 interface.The analog outputs of the TCD1304DG are compared with the analog outputs of the TCD1304DG through the AD converter.The resulting analog outputs are then transmitted to the upper computer for display.The comparison and transmission process validate the completeness and accuracy of the data, as demonstrated by Fig. 16 (the waveform detected by oscilloscope), Fig. 17

Concluding remarks
Through a series of module designs, this project provides a comprehensive description of how to efficiently and cost-effectively utilize the TCD1304DG for optical signal data processing.The primary control is accomplished through an FPGA chip, which, in comparison to traditional MCUs, eliminates the need for CPU data processing and can be understood as a targeted hardware circuit design.This characteristic grants FPGA the advantages of high flexibility, high performance, and low power consumption.Furthermore, efficient data interaction is facilitated by employing high-speed USB 3.0 data transmission, enabling a higher data transmission limit for subsequent scalable functions.With this working design, the data processing process of the spectrometer becomes more efficient and stable.
The results of this design are particularly valuable for the spectral data acquisition process in the spectrometer, as they enable the acquisition of accurate and reliable output results after wavelength calibration of the spectral data.The theoretical expectations of this design have been successfully validated, demonstrating the correctness and feasibility of the proposed approach.This work could be carried out in a variety of applications that require

Figure 4 .
Figure 4. ZYNQ A/D data conversion diagram (taken from the datasheet for the UG480 (page 34)).

Figure 13 .
Figure 13.(a) Timing diagram for synchronized slave device FIFO reads (taken from the datasheet for the Infineon-AN65974 (page 11)).(b) Synchronized slave device FIFO write timing diagram (taken from the datasheet for the Infineon-AN65974 (page 12)).

Figure 15 .
Figure 15.(a) Synchronized slave device read timing diagram.(b) Result of reading data.(c) Synchronized slave device write timing diagram.
(the data received and plotted by the host computer), and Fig.18(the data extracted from the RAM on the FPGA side and the data transmitted by the USB module).